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TV-Stereo Processor
Preliminary Data
TDA 6812-2M
Bipolar IC
Features High quality stereo signal processing High S/N ratio I2C Bus controlled Clipping detector and clock generator NICAM or AM sound inputs Volume control Universal audio interface for DOLBY, EQUALIZER, SURROUND SOUND features q Multiplex of 3-SCART connections q Independent headphones
q q q q q q q
P-MQFP-44-2
Type TDA 6812-2M
Ordering Code Q67000-A5218
Package P-MQFP-44-2
TDA 6812-2 is a complete system for stereo TV-sound, controlled by an I2C Bus. The device is made up of three functional blocks. 1. Stereo Processing with High Quality (better than DIN 45500; suitable for NICAM and CD a) Matrix for G-standard with I2C-controlled crosstalk compensation; selectable gain 0/6 dB b) Three stereo AF-inputs c) Random switching of all inputs to all outputs d) Stereo SCART-interface e) Stereo loudspeaker signal section with volume precontrol, treble/bass control, enlargement of quasi-stereo/stereo sound base, separate L/R-volume control (Vmax 10 dB), equalizer interface in front of tone control f) Stereo headphones signal section with Ch1/Ch2 and volume control 2. TV-Identification-Signal Decoder a) Active pilot-tone filter b) Phase-independent rectifier with very narrow bandwidth for identification-signal decoding c) Digital integrator for noise rejection d) Multiplexer for cyclic scanning for stereo or dual-sound identification e) Externally synchronized PLL for reference-signal generation: synchronization with line sync pulse or 62.5-kHz clock, integrated crystal oscillator and 4-MHz crystal, or with external 4-MHz timing signal
Semiconductor Group
1
08.95
TDA 6812-2M
3. Control a) I2C Bus interface with listen/talk function b) Control of entire audio processing c) Reading of clipping detector d) Control of identification-signal decoder e) Reading of identification-signal decoder f) Test modes
Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Function N.C. AF-output, equalizer, right channel AF-output, equalizer, left channel Cut-off frequency treble, left channel Cut-off frequency treble, right channel AF-output, headphones, right channel AF-output, headphones, left channel + VS (supply voltage) I2C Bus SCL I2C Bus SDA Input line sync pulse (4 x H-pulse), crystal oscillator N.C. Identification-signal decoder, filter Identification-signal decoder, filter Identification-signal decoder, PLL-filter Ground AF-input mono or left, sound 1 (adjustable) Bias AF-operating point AF-input, right, sound 2 N.C. 54-kHz input N.C. 54-kHz filter SCART-input 1, left channel
Semiconductor Group
2
TDA 6812-2M
Pin Functions (cont'd) Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function SCART-input 1, right channel SCART-input 2, left channel SCART-input 2, right channel SCART-input 3, left channel SCART-input 3, right channel AF-output SCART (mono, sound 1, left channel) AF-output SCART (mono, sound 2, right channel) Output port 1 (open collector) N.C. N.C. Output port 2 (open collector) Phase shifter quasi-stereo Phase shifter quasi-stereo Cut-off frequency bass (sound base), left channel Cut-off frequency bass (sound base), right channel AF-output, loudspeaker, right channel AF-output, loudspeaker, left channel AF-input, volume control, right channel AF-input, volume control, left channel N.C.
Semiconductor Group
3
TDA 6812-2M
Block Diagram Semiconductor Group 4
TDA 6812-2M
Circuit Description Signal Section The dematrixing and switching of multichannel TV-sound signals are performed in the matrix and switch section by the dual-carrier method. Crosstalk compensation is on the sound 1 input. The compensation stage has a range of 3 dB with a smallest increment of 0.2 dB, and gain can also be switched between 0 and 6 dB. In addition to the two inputs for the demodulated sound carriers, there are three dual-channel SCART-inputs. The two matrix AF-inputs can be bypassed internally so that decoded stereo signals of other systems (NICAM) can also be processed. The switch section terminates in the SCART-output and signal paths for the loudspeaker and headphones outputs. AF-inputs can be randomly switched to AF-outputs (8-6 matrix). In the loudspeaker signal path there is an initial volume control with a range of 0/- 15 dB and an increment of 1.25 dB. In conjunction with the main volume control that follows the tone control, very high overdriving immunity is ensured. In front of tone control there is an AF input/output interface in an equalizer or a DOLBY surround system. The switchable quasi-stereo section that follows produces a stereo listening effect for mono signals through a 180 oC phase shift at mid-range frequencies (approx. 1 kHz) in one channel. The following bass control has an increment of 3 dB in its setting range of + 15/- 12 dB. The cut-off frequency for each channel is set by an external capacitor. The circuit for enlarging the stereo sound base can be cut in for stereo signals to make the aural impression even more stereo-like by frequency-dependent antiphase crosstalk of 55 %. This works with the same cut-off frequency as the bass control, but the function is largely independent. The treble control, whose cut-off frequency is also set by an external capacitor, likewise has an increment of 3 dB in a setting range of 12 dB. The main value control with maximum gain of 10 dB, which can be adjusted separately for L and R, terminates the loudspeaker signal path. 57 steps with an increment of 1.25 dB mean a setting range of 71.25 dB. Functions like balance or loudness are implemented by software setting of the appropriate tone and volume controls. In the tone-control section there is a clipping detector that can be read on the I2C Bus and enables automatic volume correction by the controller. After each reading the clipping bit is reset, which enables a renewed check for clipping with each I2C Bus read operation. The headphones signal path includes a volume control with joint L/R-setting. 32 increments of 2 dB produce a range of 62 dB (31 x 2 dB = 62 dB). Identification-Signal Decoder The input of the identification-signal decoder consists of an operational amplifier for selectivity of the pilot tone and its sidebands with an external LC-circuit. The signal is fed to a phase-independent active bandpass filter of very narrow bandwidth (externally adjustable) that detects the presence of the lower sideband of the pilot carrier modulated with the identification signal. The center frequency of the filter is switched back and forth between dual and stereo by a multiplexer (software-controlled timing). The multiplexer halts when a sideband is detected. This first "detected" criterion is freed from noise by a digital integrator followed by a comparator and can then be read on the I2C Bus (talker) as stereo or dual mode. The C controls the signal paths. All necessary timing signals are derived from a fast settling PLL synchronized by a reference frequency. This reference must be sufficiently identical to the horizontal frequency, but no phase locking is necessary. This means that it is possible to use the crystal-controlled frequency of 62.5 kHz that is often found in PLL-tuning
Semiconductor Group
5
TDA 6812-2M
systems. As further alternatives there is an integrated crystal oscillator that requires a 4-MHz crystal, or it is possible to use a clock frequency of 1 or 4 MHz. Control Section All functions are controlled by an I2C Bus interface which can be both a listener and a talker. The currently valid data are stored in a latch block. The telegram structure is as follows: start condition - chip address - any number of bytes - stop condition The following conditions apply to the data bytes: Before the actual data byte (with setting information) a subaddress byte must always be transmitted, which the I2C Bus still interprets as a data byte. Example: Headphones (HP) volume is to be increased in several steps.
Right Start condition Chip address 84 (Hex) Subaddress volume HP 03 (Hex) Volume Step 8 08 (Hex) Subaddress volume HP 03 (Hex) Volume step 9 09 (Hex) Subaddress volume HP 03 (Hex) Volume Step 10 0A (Hex) Stop condition
Wrong Start condition Chip address 84 (Hex) Subaddress volume HP 03 (Hex) Volume Step 8 08 (Hex) Volume step 9 09 (Hex) Volume Step 10 0A (Hex) Stop condition
Different subaddresses can be used within a telegram, i.e. without a new start condition. But the change between listener and talker must always be made by stop condition - start condition - chip address. A start condition and a chip address (talk) must always be transmitted before reading. This loads the data that are to be read out on the I2C Bus interface for transfer to the C. Chip Address MSB 1 * 0 * 0 * 0 * 0 * 1 * 0 LSB R/W
R/W = 0 Read (Listen) R/W = 1 Write (Talk)
Semiconductor Group
6
TDA 6812-2M
Subaddress Bytes MSB Volume precontrol Volume left speaker Volume right speaker Volume headphones Treble/bass Switching byte I Switching byte II Switching byte III Switching byte IV Crosstalk compensation Setting Bytes a) Volume Precontrol MSB Maximum volume Max. - 1 Min. + 1 Minimum volume Power ON H= H= Q= Q= 0 1 0 1 X X X X 0 * H H H H 0 * Q Q Q Q 0 * 0 0 1 1 0 * 0 0 0 1 0 * 0 0 1 0 0 * 0 1 1 0 0 LSB X X X X 1 X X X X X X X X X X * X X X X X X X X X X * X X X X X X X X X X * X X X X X X X X X X * 0 0 0 0 0 0 0 1 1 0 * 0 0 0 0 1 1 1 0 0 1 * 0 0 1 1 0 1 1 0 0 0 LSB 0 1 0 1 0 0 1 0 1 1
Identification-signal decoder synchronization with fH = 15.625 kHz; power ON Identification-signal decoder synchronization with 4 x fH (must be 1 for operation with crystal or 4-MHz reference frequency) PLL synchronization with line sync pulse; power ON PLL synchronization with crystal oscillator (the bit for H must also be set to 1)
b) L/R-Loudspeaker Volume MSB Maximum volume Max. - 1 Max. - 15 Minimum volume Power ON X X X X 0 * X X X X 0 * 1 1 1 0 0 * 1 1 1 0 0 * 1 1 0 1 0 * 1 1 0 0 0 * 1 1 0 0 0 LSB 1 0 0 0 1
Semiconductor Group
7
TDA 6812-2M
c) Headphones Volume MSB Maximum volume Max. - 1 Max. - 15 Max. - 31 Power ON T2 T2 T2 T2 0 * T1 T1 T1 T1 0 * T0 T0 T0 T0 0 * 1 1 1 0 0 * 1 1 0 0 0 * 1 1 0 0 0 * 1 1 0 0 0 LSB 1 0 0 X 1
T0, T1 and T2 are test bits and must be set to 0 for normal operation. d) Crosstalk Compensation Matrix (sound 1) MSB Maximum gain Max. - 1 Gain 0 dB Minimum gain Minimum gain Power ON e) Treble / Bass MSB Linear Max. treble, lin. bass Max. treble, lin. bass Min. treble, lin. bass Min. treble, lin. bass Lin. treble, max. bass Lin. treble, max. bass Lin. treble, max. bass Lin. treble, min. bass Lin. treble, min. bass Max. treble, max. bass Min. treble, min. bass Power ON 1 1 1 0 0 1 1 1 1 1 1 0 0 MSB treble * 0 1 1 1 0 0 0 0 0 0 1 0 0 * 0 0 X 0 X 0 0 0 0 0 X X 0 * 0 0 X 0 X 0 0 0 0 0 X X 0 LSB treble * 1 1 1 1 1 1 1 1 0 0 1 0 0 MSB bass * 0 0 0 0 0 1 1 1 1 0 1 0 0 * 0 0 0 0 0 0 X 1 0 X X X 0 LSB 0 0 0 0 0 1 1 X 0 X 1 X 1 LSB bass X X X X X X * X X X X X X * X X X X X X * 1 1 1 0 0 0 * 1 1 0 0 0 0 * 1 1 0 0 0 0 * 1 1 0 0 0 0 LSB 1 0 0 1 X 1
Semiconductor Group
8
TDA 6812-2M
f) Switching Bytes I, II, III Switching Byte I Switching byte II Switching byte III MSB L3 0 * L2 0 * L1 0 SCART-output Headphones output Loudspeaker output * L0 0 * R3 0 * R2 0 * R1 0 LSB R0 1 Power ON
L0 thru L3 left output, R0 thru 3 right output.
L3 0 0 0 0 0 0 0 0 1 1
L2 0 0 0 0 1 1 1 1 0 0
L1 0 0 1 1 0 0 1 1 0 0
L0 0 1 0 1 0 1 0 1 0 1
Selected Input MUTE AF-input left, mono, sound 1 AF-input right, sound 2 AF-input left, dematrixed SCART 1 left SCART 1 right SCART 2 left SCART 2 right SCART 3 left SCART 3 right
Assignment R3 thru R0 is identical to L3 thru L0.
Semiconductor Group
9
TDA 6812-2M
g) Switching Byte IV MSB MPX0 * MPX1 * QSt * BE * Mono * P1 * P2 LSB Matrix
MPX0 0 0 1
MPX1 0 1 0
MPX-Period 2s 4s 8s Power-ON
Recommended C13,14 1 F 2.2 F 4.7 F
Perm. Xtal Tolerances 20 ppm 10 ppm 5 ppm
Settings specially recommended for crystal operation 0 0 0 1 2s 4s 470 nF 330 nF 40 ppm 70 ppm
MXP-period = 2 s means that identification-signal decoder searches 1 s for dual and 1 s for stereo. It is basically permissible, for the given C13,14, to make the MPX period longer, but not shorter. QSt QSt BE BE Mono Mono P1 P1 P2 P2 Matrix Matrix = = = = = = = = = = = = 0 1 0 1 0 1 0 1 0 1 0 1 Quasi-stereo OFF; power ON Quasi-stereo ON Stereo base enlargement OFF; power ON Stereo base enlargement ON Identification-signal decoder set to mono and held; power ON Normal operation of identification-signal decoder Port 1 (open collector) low (low-impedance); power ON Port 1 high (high impedance) Port 2 (open collector) low (low-impedance); power ON Port 2 high (high impedance) Gain matrix 0 dB Gain matrix 6 dB; power ON
h) Talk Mode MSB St 0 1 0 1 CL = 1 * D 0 0 1 1 * T3 * T4 * T5 * CL * X LSB X
Decoder detects mono Decoder detects stereo Decoder detects dual Suppressed internally
Loudspeaker signal path at clipping limit (CL is automatically reset after each reading operation)
T3 thru T5 are test bits.
Semiconductor Group
10
TDA 6812-2M
Absolute Maximum Ratings TA = 0 to 70 oC; all voltages relatives to VSS Parameter Supply voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Symbol Limit Values min. max. 14 V V V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unit Remarks
V8 V4 V5 V9 V10 V13 V14 V17 V18 V19 V21 V24 V25 V26 V27 V28 V29 V32 V35 V36 V37 V38 V39 V42 V43 I2 I3 I6 I7 I11 I15 I23 I30 I31 I40 I41
V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8 V8
2 2 2 2 2 1 2 2 2 2 2
Semiconductor Group
11
TDA 6812-2M
Absolute Maximum Ratings (cont'd) TA = 0 to 70 oC; all voltages relatives to VSS Parameter ESD-voltage ESD-voltage Junction temperature Storage temperature Thermal resistance system ambient Operating Range Supply voltage Ambient temperature Input frequency range Symbol Limit Values min. max. 2 6 150 - 40 125 55 kV kV
oC oC
Unit
Remarks HBM (R = 1.5 k, C = 100 pF) HBM (R = 1.5 k, C = 100 pF)
VESD
-2
VESD24-31 - 6 Tj Tstg R th SA
K/W
V8 TA fI
10 0 0.01
13.2 70 20
V
oC
kHz
Semiconductor Group
12
TDA 6812-2M
Characteristics
VS = 12 V; TA = 25 oC; AF-reference level 0 dB = 100 mVrms unless otherwise defined; in
accordance with test circuit 1. I2C Bus preset: Start - 84 - 01,3F - 02,3F - 00,00-03,1F - 04,88 - 05,10 - 06,12-07,12-08,12-09,00-Stop Chip address - Vol LSl 63 - Vol LSr 63 - Vol Pre 0 - Vol HP 31 - Tone lin - Gain 0 dB - Switch byte I, II, II, IV The basic setting for each item in the specifications is always preset; the test conditions only state settings that differ. Details in italics are for explanation of the hex codes, for switching bits only set bits or functions are given.
Parameter
Symbol
Limit Values min. typ. 58 max. 85
Unit
Test Condition Test all datas page 13 to 20 Circuit are applied to test circuit 1
Current consumption I8 Signal Section Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Gain Gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Gain Gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain
mA
V41-17 V40-19 V3-17 V2-19 V7-17 V6-19 V30-17 V31-19 V41-19 V40-19 V3-19 V2-19 V7-19 V6-19 V41-17 V3-17 V7-17 V30-19 V30-17 V41-17 V40-19 V3-17 V2-19 V7-17 V6-19
8 8 -2 -2 -2 -2 -2 -2 8 8 -2 -2 -2 -2 14 4 4 -2 4 14 14 4 4 4 4
10 10 0 0 0 0 0 0 10 10 0 0 0 0 16 6 6 0 6 16 16 6 6 6 6
12 12 2 2 2 2 2 2 12 12 2 2 2 2 18 8 8 2 8 18 18 8 8 8 8
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 08,32; Stereo; V17 = 0 08,32; Stereo; V17 = 0 08,32; Stereo; V17 = 0 08,32; Stereo; V17 = 0 07,32; Stereo; V17 = 0 07,32; Stereo; V17 = 0 08,32; Stereo; V19 = 0 08,32; Stereo; V19 = 0 07,32; Stereo; V19 = 0 06,32; Stereo; V17 = 0 06,32; Stereo; V19 = 0 09,01; 6 dB 09,01; 6 dB 09,01; 6 dB 09,01; 6 dB 09,01; 6 dB 09,01; 6 dB
Semiconductor Group
13
TDA 6812-2M
Characteristics (cont'd) Parameter Gain Gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Gain Gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Gain Gain Symbol Limit Values min. typ. 6 6 16 16 6 6 6 6 22 12 12 6 12 10 10 0 0 0 0 0 0 max. 8 8 18 18 8 8 8 8 24 14 14 8 14 12 12 2 2 2 2 2 2 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 09,01; 6 dB 09,01; 6 dB 08,32-09,01; V17 = 0 Stereo; 6 dB 08,32-09,01; V17 = 0 Stereo; 6 dB 08,32-09,01; V17 = 0 Stereo; 6 dB 08,32-09,01; V17 = 0 Stereo; 6 dB 07,32-09,01; V17 = 0 Stereo; 6 dB 07,32-09,01; V17 = 0 Stereo; 6 dB 08,32-09,01; V19 = 0 Stereo; 6 dB 08,32-09,01; V19 = 0 Stereo; 6 dB 07,32-09,01; V19 = 0 Stereo; 6 dB 06,32-09,01; V17 = 0 Stereo; 6 dB 06,32-09,01; V19 = 0 Stereo; 6 dB 08,45; SCART 08,45; SCART 08,45; SCART 08,45; SCART 07,45; SCART 07,45; SCART 06,45; SCART 06,45; SCART 4 4 14 14 4 4 4 4 20 10 10 4 10 +8 +8 -2 -2 -2 -2 -2 -2 Unit Test Condition Test Circuit
V30-17 V31-19 V41-19 V40-19 V3-19 V2-19 V7-19 V6-19 V41-17 V3-17 V7-17 V30-19 V30-17 V41-24 V40-25 V3-24 V2-25 V7-24 V6-25 V31-24 V31-25
Same values apply for pins 26 thru 29
Semiconductor Group
14
TDA 6812-2M
Characteristics (cont'd) Parameter Min. gain main control Min. gain main control Min. gain precontrol Min. gain precontrol Min. gain Min. gain Tracking error Symbol Limit Values min. typ. - 60 - 60 -7 -7 -5 -5 max. - 55 - 55 -3 -3 dB dB dB dB 01,08-02,08 Vol LSl 8-Vol LSr 8 01,08-02,08 Vol LSl 8-Vol LSr 8 00,18 Vol Pre 24 00,18 Vol Pre 24 03,01; Vol HP 1 03,01; Vol HP 1 01,3F-01,24 02,3F-02,24 Vol LSl 63-36-Vol LSr 63-36 03,1F-03,13 Vol HP 31-19 01,X-01, (X 1) Vol LSl X-Vol LSl (X 1) 02,X-02, (X 1) Vol LSr X-VolLSr (X 1) 00,X-00, (X 1) VolPre X-Vol Pre (X 1) 00,X-00, (X 1) Vol Pre X-Vol Pre (X 1) 03,X-03, (X 1) Vol HP X-Vol HP (X 1) 03,X-03, (X 1) Vol HP X-Vol HP (X 1) 05,1F; Gain max 05,1F; Gain max 05,1F; Gain max 05,01; Gain min 05,01; Gain min 05,01; Gain min Unit Test Condition Test Circuit
V41-17 V40-19 V41-17 V40-19
Same values apply for pins 24 thru 29
V7-17 V6-19
V40-41 V6-7 V41 V40 V41 V40 V6 V7 0 0 0 0 0 0 2.5 2.5 2.5 - 3.5 - 3.5 - 3.5
- 62 - 62
- 57 - 57 2 2
dB dB dB
Same values apply for pins 24 thru 29
Tracking error Increment Vol 41 Increment Vol 40 Increment Vol 41 Increment Vol 40 Increment Vol 6 Increment Vol 7 Matrix adjustment Matrix adjustment Matrix adjustment Matrix adjustment Matrix adjustment Matrix adjustment
dB dB dB dB dB dB dB dB dB dB dB dB dB
1.25 1.25 1.25 1.25 2 2 3 3 3 -3 -3 -3
2.5 2.5 2.5 2.5 4 4 3.5 3.5 3.5 - 2.5 - 2.5 - 2.5
V41-17 V7-17 V30-17 V41-17 V7-17 V30-17
Semiconductor Group
15
TDA 6812-2M
Characteristics (cont'd) Parameter Adj. increment Adj. increment Adj. increment Bass boost Bass boost Bass cutoff Bass cutoff Increment bass Increment bass Treble boost Treble boost Treble cut-off Treble cut-off Increment treble Increment treble Sound linearity Symbol V41 V7 V30 0.1 0.1 0.1 13 13 Limit Values min. typ. 0.2 0.2 0.2 15 15 - 12 - 12 1 1 10 10 3 3 12 12 - 12 - 12 1 1 3 3 5 5 2 2 5 5 max. 0.3 0.3 0.3 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 05,X-05, (X 1) Gain X-Gain (X 1) 05,X-05, (X 1) Gain X-Gain (X 1) 05,X-05, (X 1) Gain X-Gain (X 1) 04,8F; f I = 40 Hz Bass max, Treble lin 04,8F; f I = 40 Hz Bass max, Treble lin 04,80; f I = 40 Hz Bass min, Treble lin 04,80; f I = 40 Hz Bass min, Treble lin 04,8X-04.8 (X 1) Bass X-Bass (X 1) 04,8X-04.8 (X 1) Bass X-Bass (X 1) 04,8F; f I = 15 kHz Treble max, Bass lin 04,8F; f I = 15 kHz Treble max, Bass lin 04,8F; f I = 15 kHz Treble min, Bass lin 04,8F; f I = 15 kHz Treble min, Bass lin 04,8X-04, (X 1) 8 Treble X-Treble (X 1) 04,8X-04, (X 1) 8 Treble X-Treble (X 1) 04,88; Unit Test Condition Test Circuit
V7-17 V40-19 V7-17 V40-19
V40 V41
V41-17 V40-19 V41-17 V40-19
V40 V41 V40 V41
f I = 40 Hz - 15 kHz
Sound linearity dB
Treble, Bass lin 04,88; f I = 40 Hz - 15 kHz Treble, Bass lin
Semiconductor Group
16
TDA 6812-2M
Characteristics (cont'd) Parameter Symbol Limit Values min. Response threshold V17 of clipping detector typ. 580 max. mVrms 04,8F; fI = 40 Hz Treble lin, Bass max 01,2F-02,2F Vol LSl 47-Vol LSr 47 dB dB dB dB Unit Test Condition Test Circuit
Same values apply for pins 19 and 24 thru 29 Channel separation V40-41 50 Channel separation V6-7 50 Channel separation V30-31 50 Crosstalk attenuation Muting attenuation Muting attenuation Muting attenuation Muting attenuation Muting attenuation Muting attenuation Muting attenuation Muting attenuation IN/OW 60
V19 or V17 = 200 mVrms V19 or V17 = 200 mVrms V19 or V17 = 200 mVrms VIW = 0; VIN17,19 = 600 mVrms; VIN24-29 = 2 Vrms
08,0X; V17 = 600 mVrms MUTE L 08,X0; V19 = 600 mVrms MUTE R 08,0X; V17 = 600 mVrms MUTE L 08,X0; V19 = 600 mVrms MUTE R 07,0X; V17 = 600 mVrms MUTE L 07,X0; V19 = 600 mVrms MUTE R 06,X0; V19 = 600 mVrms MUTE R 06,0X; V17 = 600 mVrms MUTE L
17-41 19-40 17-3 19-2 17-7 19-6 19-31 17-30
80 80 80 80 80 80 80 80
dB dB dB dB dB dB dB dB
Same values apply for pins 24 thru 29; V24-29 = 2 Vrms Max. input voltage Max. input voltage Max. input voltage Max. input voltage Max. input voltage Max. input voltage
V19* V17 V17 V19* V17 V17
600 600 300 300 300 150
mVrms mVrms mVrms mVrms mVrms mVrms
V40 1 % V41 1 % V41 1 %; stereo V40 1 %; 09,01; 6 dB V41 1 %; 09,01; 6 dB V41 1 %; 09,01; 6 dB; stereo
* VIN in mono mode without SC2 V19 = 2 Vrms resp. 1 Vrms
Semiconductor Group
17
TDA 6812-2M
Characteristics (cont'd) Parameter Max. input voltage Max. input voltage Max. input voltage Max. input voltage
1)
Symbol
Limit Values min. typ. max. 2.4 2.4
Unit Vrms Vrms Vrms Vrms
Test Condition
Test Circuit
V42 V43 V24 V251)
1)
V40 1 %; 01,37; 02,37 V41 1 %; Vol SPL SS;
Vol SPR SS V41 3 % V40 3 %
2 2
Full tone control possible when 00,18; Vol Pre 24 Same values apply for pins 26 thru 29 Distortion factor Distortion factor Distortion factor Distortion factor
THD6 THD7 THD6 THD7
0.01 0.01 0.01 0.01
0.1 0.1 0.1 0.1
% % % %
V19 = 250 mVrms V17 = 250 mVrms V19 = 250 mVrms; 03,15
Vol HP 21 V19 = 250 mVrms; 03,15 Vol HP 21
Same values apply for pins 24 thru 29; V24-29 = 600 mVrms Distortion factor Distortion factor Distortion factor
THD41 THD40 THD41 THD40 THD41 THD40
0.01 0.01 0.01
0.1 0.1 0.2
% % %
V17 = 100 mVrms V19 = 100 mVrms V17 = 0.1 Vrms
01,2F-02,2F Vol LSl 47-Vol LSr 47 V19 = 0.1 Vrms 01,2F-02,2F Vol LSl 47-Vol LSr 47 V17 = 80 mVrms; 04,XX Tone random V19 = 80 mVrms; 04,XX Tone random
Distortion factor
0.01
0.2
%
Distortion factor Distortion factor
0.10 0.10
0.4 0.4
% %
Same values apply for pins 24 thru 29; V24-29 = 600 mVrms Distortion factor Distortion factor
THD31 THD30
0.01 0.01 0.55
0.1 0.1
% %
V19 = 250 mVrms V17 = 250 mVrms V19 = 600 mVrms; fI = 2 kHz; 09,10
Base V17 = 600 mVrms; fI = 2 kHz; 09,10 Base
Same values apply for pins 24 thru 29; V24-29 = 600 mVrms Antiphase crosstalk V41-40 0.5 sound base Antiphase crosstalk V40-41 0.5 sound base Sound base phase 40-41 Sound base phase 41-40 150 150
0.55
180 180
210 210
deg deg
V17 = 600 mVrms; 09,10
Base; f = 2 kHz V19 = 600 mVrms; 09,10 Base; f = 2 kHz
Semiconductor Group
18
TDA 6812-2M
Characteristics (cont'd) Parameter Phase rotation quasi stereo Symbol Limit Values min. 41-40 41-40 41-40 Unweighted SNR Unweighted SNR Unweighted SNR S/N41 S/N40 S/N41 60 0 130 - 30 typ. 10 180 10 85 85 70 max. 40 230 0 94 94 deg deg deg dB dB dB Unit Test Condition Test Circuit
V19,17 = 600 mVrms; 09,20; QSt; f = 40 Hz V19,17 = 600 mVrms; 09,20; QSt; f = 700 Hz V19,17 = 600 mVrms; 09,20; QSt; f = 15 kHz VNrms 20 Hz-20 kHz ; V17 = 0.6 Vrms VNrms 20 Hz-20 kHz ; V19 = 0.6 Vrms VNrms 20 Hz-20 kHz ; V17 = 0.6 Vrms
01,27-02,27 Vol LSl 39-Vol LSr 39 VNrms 20 Hz-20 kHz ; V19 = 0.6 Vrms 01,27-02,27 Vol LSl 39-Vol LSr 39
Unweighted SNR
S/N40
60
70
dB
Noise voltage
VN41 VN40
36
100
Noise voltage
36
100
Vrms VNrms 20 Hz-20 kHz ; 01,00-02,00 Vol LSl 0-Vol LSr 0 Vrms VNrms 20 Hz-20 kHz ; 01,00-02,00 Vol LSl 0-Vol LSr 0 dB dB dB
Unweighted SNR Unweighted SNR Unweighted SNR
S/N7 S/N6 S/N7 S/N6 65
85 85 70
94 94
VNrms 20 Hz-20 kHz ; V17 = 0.6 Vrms VNrms 20 Hz-20 kHz ; V19 = 0.6 Vrms VNrms 20 Hz-20 kHz ; V17 = 0.6 Vrms
03,10; Vol HP 16
Unweighted SNR
65
70
dB
VNrms 20 Hz-20 kHz ; V19 = 0.6 Vrms
03,10; Vol HP 16
Noise voltage Noise voltage
VN7 VN6
12 12
33 33
Vrms VNrms 20 Hz-20 kHz ; 03,00; Vol HP 0 Vrms VNrms 20 Hz-20 kHz ; 03,00; Vol HP 0
Semiconductor Group
19
TDA 6812-2M
Characteristics (cont'd) Parameter Unweighted SNR Unweighted SNR Symbol S/N30 S/N31 Limit Values min. typ. 90 90 70 70 70 70 70 70 12 12 12 12 60 60 12 12 max. 97 97 dB dB dB dB dB dB dB dB mV mV mV mV mV mV mV mV Unit Test Condition Test Circuit
VNrms 20 Hz-20 kHz ; V17 = 0.6 Vrms VNrms 20 Hz-20 kHz ; V19 = 0.6 Vrms
01,55-02,55 Vol LSl 55, Vol LSr 55 Vripple = 1 Vrms fripple = 50 Hz - 20 kHz Rgen (Pin 17,19) = 220 Unweighted 20 Hz - 20 kHz 01,X-01,X 1 Vol LSl X-Vol LSl (X 1) 02,X-02, X 1 Vol LSr X-Vol LSr (X 1) 00,X-04, X 1 Vol Pre X-Vol Pre (X 1) 00,X-04, X 1 Vol Pre X-Vol Pre (X 1) 04,X-05, X 1 Tone X-Tone (X 1) 04,X-05, X 1 Tone X-Tone (X 1) 03,X-03, X 1 Vol HP X-Vol HP (X 1) 03,X-03, X 1 Vol HP X-Vol HP (X 1) 1
Power supply ripple PSRR30 rejection (PSRR) PSRR31 PSRR40 PSRR41 PSRR6 PSRR7 DC pop 1 bit DC pop 1 bit DC pop 1 bit DC pop 1 bit DC pop 1 bit DC pop 1 bit DC pop 1 bit DC pop 1 bit V41 V40 V41 V40 V41 V40 V6 V7
1
Semiconductor Group
20
TDA 6812-2M
Characteristics (cont'd) Parameter Symbol Limit Values min. Design-Related Data Input resistance Input resistance Input resistance Input resistance Input resistance Input resistance Input resistance Input resistance Input resistance Input resistance Output resistance Output resistance Output resistance Output resistance Output resistance Output resistance Output resistance Output resistance typ. max. k k k k k k k k k k 70 70 70 70 70 70 70 70 Unit Test Condition Test Circuit
R 17 R 19 R 24 R 25 R 26 R 27 R 28 R 29 R 42 R 43 R2 R3 R6 R7 R 30 R 31 R 40 R 41
22 22 40 40 40 40 40 40 30 30
Semiconductor Group
21
TDA 6812-2M
Characteristics (cont'd) Parameter Symbol min. Identification-Signal Decoder Gain filter op-amp Max. input voltage VCO voltage PLL VCO voltage PLL VCO voltage PLL VCO voltage PLL Limit Values typ. max. Unit Test Condition Test Circuit
V23 V23 V15 V15 V15 V15 V15 V15
2
13 600 1.3 2
14
15
dB mVpp V
VIF = 80 mVpp
Function
1 2 2 2 2 2
3
4 4.7
V V V
1.3
f 11 = 14.6 kHz; V11 = 2.5 V f 11 = 15.625 kHz; V11 = 2.5 V f 11 = 16.6 kHz; V11 = 2.5 V f 11 = 58.4 kHz; V1 = 2.5 V
VCO voltage PLL
4.7
V
VCO voltage PLL
2
3
2
4
V
2 00,40, Line sync f 11 = 66.4 kHz; V11 = 2.5 V 00,40, Line sync 00,40, Line sync; Xtal 4
V ID filter
V 13 - V 13 + V 14 - V 14 V13 resp. V14 when V23 = 0 = --------------------------------------------------------------------------------- V13* resp. V14* when V23 = 100 mVpp; m = 50 % V 23
VISF VISF
3.4 6.8 dB
f 23 = pilot signal:
Gain identificationsignal filter Gain identificationsignal filter
2
dual I2C-talk: dual 3.4 6.8 dB
f 23 = pilot signal:
2
stereo; I C-talk: stereo
2
V13 test = V13 (V21 = 0) V13 ; V14 test = V14 (V23 = 0) V14
Detection threshold Detection threshold Detection threshold Detection threshold V13 - V13 V4 - V14 900 900 900 900 mV mV mV mV I2C-talk: stereo or dual I2C-talk: stereo or dual I2C-talk: stereo or dual I2C-talk: stereo or dual 3 3 3 3
Semiconductor Group
22
TDA 6812-2M
Characteristics (cont'd) Parameter Mono threshold Mono threshold Mono threshold Mono threshold Detection response Detection response Symbol min. V13 - V13 V14 - V14 0 0 0 0 0.25 0.25 0 3.5 0.3 2 0.29 0.35 2.17 4.34 8.68 0.42 Limit Values typ. max. 100 100 100 100 0.5 0.5 1.5 mV mV mV mV I2C-talk: mono I2C-talk: mono I2C-talk: mono I2C-talk: mono I2C-talk: stereo or dual; V13 = 1 V I2C-talk: stereo or dual; V14 = 1 V Unit Test Condition Test Circuit 3 3 3 3 3 3 2 2
tdet tdet
tMPX tMPX
V V Vpp Vpp
VH-IL Switching threshold f REF-input Switching VH-IH threshold f REF-input
Amplitude crystal oscillator External 1-MHz or 4-MHz clock Crystal current Multiplexer clock Multiplexer clock Multiplexer clock Design-Related Data Filter output resistance
V8
V11* V11 I11 tMPX tMPX tMPX
fO = 4.00000 MHz
Series resonance
4 3
mArms RQ = 40 s 09,08, MPX = 2 s s 09,48, MPX = 4 s s 09,88, MPX = 8 s
R 13,14 R 11 Z 11
R Q1 R Q3
110 800 - 600 - 500 - 400 100 300 20
k dB Ptot QU = 1W; 4 MHz Ptot QU = 1W; 12 MHz Ptot QU = 1W; f <15 MHz
f REF input
resistance Input impedance crystal oscillator Crystal oscillator series resistance Crystal oscillator series resistance Spurious harmonic ratio
Semiconductor Group
23
TDA 6812-2M
Characteristics (cont'd) Parameter Symbol min. I2C Bus (SCL, SDA) Edges SCL, SDA Rise time Fall time Shift register clock SCL Frequency H-pulse width L-pulse width Start Setup time Hold time Stop Setup time Bus free Data change Setup time Hold time Input SCL, SDA Input voltage Input current Output SDA (open collector) Output voltage Output voltage port 1 Output voltage port 1 Limit Values typ. max. Unit Test Condition Test Circuit
tR tF
1 300
s ns
f SCL tH tL tSUSTA tHDSTA tSUSTO tBUF tSUDAT tHDDAT VQH VQL IQH IQL VQH VQL V32H V32L V35H V35L
0 4 4 4 4 4 4 1 300 3
100
kHz s s s s s s s ns
5.5 1.5 50 100
V V A A V V V V V V
5.4 0.4
R L = 2.5 k IQL = 3 mA R L = 2.5 k; 09,04 IQL = 3 mA; 09,00 R L = 2.5 k; 09,02 IQL = 3 mA; 09,00
2 2 2 2
VS
0.4
VS
0.4
Semiconductor Group
24
TDA 6812-2M
Test Circuit 1 Semiconductor Group 25
TDA 6812-2M
Test Circuit 2 Semiconductor Group 26
TDA 6812-2M
Test Circuit 3 Semiconductor Group 27
TDA 6812-2M
Test Circuit 4 Semiconductor Group 28
TDA 6812-2M
Application Circuit 1 Semiconductor Group 29
TDA 6812-2M
Application Circuit 2 Semiconductor Group 30
TDA 6812-2M
TV-Soundconcept with Dolby-Surround-Option
Semiconductor Group
31
TDA 6812-2M
Application Circuit 3 with Dolby-Surround-Option Semiconductor Group 32
TDA 6812-2M
I2C Bus Timing Diagram
tSUSTA tHDSTA tH tL tSUDAT tHDDAT tSUSTO tBUF tF tR
Setup time (start) Hold time (start) H-pulse width (clock) L-pulse width (clock) Setup time (data change) Hold time (data change) Setup time (stop) Bus free time Fall time Rise time
All times referred to VIH and VIL values.
Semiconductor Group
33
TDA 6812-2M
Package Outlines
Plastic-Package, P-MQFP-44-2 (SMD) (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 34
Dimensions in mm
GPM05622

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